The present invention relates to Silicon-on-Insulator devices and, more particularly, to Silicon-on-Insulator devices having suppressed floating body effects.
Integrated Circuits (IC) containing Silicon On Insulator (SOI) devices are becoming increasingly important due to their speed. An SOI device (i.e., transistor) is typically formed in a layer of semiconductor material overlaying an insulating layer formed in a semiconductor substrate.
A prior art SOI transistor such as that shown in FIG. 1 includes a source region 14 and a drain region 14 which are separated from each other by a channel region 12. A gate 15 is separated from the device by a gate oxide layer 13. Both the source and drain regions are of the same conductivity type opposite to that of the body region 16. For example, when the body region is of a p-type material, the source and drain regions are of n-type materials. The source and drain regions typically have a higher dopant concentration level than the body region.
There are two known types of SOI transistors, namely partially depleted SOI transistor and fully depleted SOI transistor.
In a partially depleted SOI transistor, such as the known SOI transistor 10 of FIG. 1, when channel 12 is formed between source/drain regions 14, depletion region 16 extends only partially into body layer 18. Unlike a conventional MOS transistor, a typical SOI transistor, such as SOI transistor 10, does not have a body contact. In other words, body layer 18 of SOI 10 floats. Consequently, when a DC current flows between the source and drain regions 14, holes generated due to impact ionization, thermal effects or gate-induced drain leakage, flow to the floating body layer 18 thereby affecting its potential and causing its threshold voltage to change (i.e., due to the transistor body effect). Similarly, when the gate or source/drain voltage is modulated (i.e. during transient events), the potential at body layer 18 is changed, which modulates the SOI threshold voltage.
In a fully depleted SOI, such as the known SOI 20 of FIG. 2, the width of body layer 22 overlaying insulating layer 24 is smaller than the width of the depletion region that extends into body layer 18 when channel 12 is formed. Therefore, the potential at body layer 18 remains fixed. Accordingly, the threshold voltage of SOI transistor 20 remains unchanged and is not subject to the body effect.
Although SOI 20 does not suffer from threshold voltage variations due to body effect, it is difficult to controllably manufacture a thin body layer 22 that fully depletes when channel 12 is formed.
Therefore, a need continues to exists for an SOI device which has a suppressed body-effect and which can be controllably manufactured.
A Silicon-on-Insulator (SOI) transistor, in accordance with one embodiment of the present invention, includes an intrinsic body layer in which source and drain regions are formed; a shallow p-type pocket adjacent the source region and a shallow p-type pocket adjacent the drain region. The shallow p-type pockets increase the threshold voltage of the SOI device. Because the body layer is lightly doped, it is fully depleted when the device channel is formed. Some embodiments of the present invention include two deep p-type pockets. The first deep p-type pocket is adjacent the source and its neighboring shallow p-type pocket. The second deep p-type pocket is adjacent the drain and its neighboring shallow p-type pocket. The deep p-type pockets suppress the punch-through current.